1. Field of the Invention
The invention relates to integrated circuits, and more particularly to a mechanism for testing and fine-tuning the signal quality of integrated circuit (IC) chips.
2. Description of the Related Art
In computer systems, the general method for improving the data transfer rate is to raise the bus frequency or increase the data bus width. Growing bus width significantly increases the I/O density of IC chips. Although this is a common method in recent years, a great increase in the I/O density causes computer systems to be more susceptible to electromagnetic interference (EMI) caused by higher frequencies, and presents a difficult challenge in IC design, board layout and PCB manufacture.
Today, the most commonly encountered noise problems in high-speed systems are ground bounce and power bounce. The basic form of ground or power bounce occurs when the IC chip has multiple output pins changing state simultaneously. Such bounce types are referred to as simultaneous switching output (SSO) noise. For example, the least significant bit (LSB) of an 8-bit output is in the low state and the others are switching from high to low, that is, from “11111110” to “00000000”. This creates an induced voltage across the parasitic inductance in the ground lead of the IC chip. Because the parasitic inductance is between the external system ground and the internal IC chip ground, the induced voltage causes the internal ground to be at a different potential than the external ground. This induced voltage is known as ground bounce as shown in FIG. 1. In this case, ground bounce on the LSB in the low state may be substantial enough to cross the input threshold of a subsequent device, which in turn can cause this device to misinterpret the static LSB as a logic “1”. Power ground is the inverse of ground bounce. For example, the most significant bit (MSB) of an 8-bit output is in the high state and the others are switching from low to high, that is, from “10000000” to “11111111”. This creates an induced voltage across the parasitic inductance in the power lead of the IC chip. FIG. 2 shows an exemplary graph of power bounce. In this case, power bounce on the MSB in the high state may be substantial enough to drop below the input threshold of a subsequent device, which in turn can cause this device to misinterpret the static MSB as logic “0”.
Ground and power bounce problems can result in the unexpected, unreliable, and sometimes intermittent, behavior of a computer system. As data transfer rate increases, SSO noise becomes a crucial issue for high-speed IC design. Therefore, what is needed is a way for IC chips to quickly detect and effectively defeat SSO noise.